Package substrates with multiple dice

ABSTRACT

This disclosure relates generally to package substrates with multiple embedded dice wherein each of the embedded dice can be connected directly to a bus of the package substrate without being routed through another die. The package substrate may be configured as a bumpless build up layer (BBUL) substrate.

TECHNICAL FIELD

The disclosure herein relates generally to semiconductor dice and diepackages.

BACKGROUND ART

Stacked die semiconductor configurations may use connector pathways thatpass through one or more dice to transmit data or connect power to thedice. As the scale of semiconductor devices continually shrinks,efficient designs are desired to improve signals and powertransmissions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a die assembly according to an exampleembodiment.

FIG. 2 is a block diagram of a multiple die assembly according to anexample embodiment.

FIG. 3 is a block diagram of another multiple die assembly according toan example embodiment.

FIG. 4 is a block diagram of another multiple die assembly according toan example embodiment.

FIG. 5 is a block diagram of another multiple die assembly according toan example embodiment.

FIG. 6 is a flow diagram of a method according to an example embodiment.

FIG. 7 is a block diagram of an electronic device according to anexample embodiment.

DESCRIPTION OF THE EMBODIMENTS

The following description and the drawings sufficiently illustratespecific embodiments to enable those skilled in the art to practicethem. Other embodiments may incorporate structural, logical, electrical,process, or other changes. Portions and features of some embodiments maybe included in, or substituted for, those of other embodiments.Embodiments set forth in the claims encompass all available equivalentsof those claims.

FIG. 1 is an illustration of an embedded die assembly 100. The embeddeddie assembly 100 consists of a package substrate 102, a first die 104, asecond die 106, and a number of connections 108. A connection 110 may berouted through the first die 104 to connect from the second die 106 to abus 112 in the package substrate 102. Thus, a connection 110 passesthrough the first die 104. Having the connection 110 through the firstdie 104 may eliminate valuable space in the first die 104 and maycomplicate routing. Having the connection 110 through the first die 104may cause unwanted electrical interference with data signals. Aconnection such as connection 110 may be a through silicon via (TSV). ATSV is limited in the amount of power that can be transmitted due togeometry available with known manufacturing methods. It is desired tohave a device that can have multiple dice embedded in a packagesubstrate wherein all of the dice can connect directly to the packagesubstrate without using connections routed through a die in a packagesubstrate.

FIG. 2 is an illustration of a device 200 according to an exampleembodiment. Device 200 may include first and second dice 204 and 206 andat least one first die to substrate connection 208, at least one seconddie to substrate connection 210, and at least one second die to firstdie connection 212 included in a package substrate. In certain examples,the first and second dice 204 and 206 are flip-chip dice.

In certain examples, package substrate 202 may be a bumpless build-uplayer (BBUL) package substrate, with one or more of the dice 204, 206embedded in the package substrate. A BBUL package substrate includes adie or dice embedded in a substrate, which has one or more build-uplayers formed underneath the die. In certain examples, a standard microvia formation process such as laser drilling may form connectionsbetween build-up layers and die or dice bond pads. The build-up layersmay be formed using a standard high-density integration patterningtechnology.

Package substrate 202 may include the first and second dice 204 and 206embedded therein. In certain examples, the second die 206 may be stackedon the first die 204 at a top surface of the first die. In certainexamples, the second die 206 may be coupled to the first die 204 at atop surface of the first die. The first or second dice 204 or 206 may beanalog, digital, or a combination thereof. An analog die is a die whichuses predominately analog components, whereas a digital die is a diewhich uses predominately digital components. Some examples of types ofdice are memory, radio, processor, arithmetic unit, or any combinationthereof, among many others.

Package substrate 202 may include one or more buses. In the illustratedexample of FIG. 2, package substrate 200 includes two buses 214 a and214 b. Buses 214 a or 214 b may include a power bus or a data bus. Incertain examples, bus 214 a is a power bus and bus 214 b is a groundbus. In certain examples, bus 214 a is a power bus and bus 214 b is adata bus.

The second die 206 may include a footprint that includes a dimension(e.g. a width) that is larger than a corresponding dimension of afootprint of the first die 204. In certain examples, the largerdimension of the second die 206 may allow for connections between thesecond die 206 and the package substrate outside the periphery of thefirst die 204, without requiring a TSV. Including a second die 206 thathas a larger footprint than a first die 204, at least in one dimension,may allow cost savings by dividing circuitry between each die based uponhow well they scale/reduce in size with fabrication processes. Forexample, the use of a lower cost technology for circuitry that does notscale well into the reduced size, higher cost technology fabricationprocesses may be used to make the second die 206, and newer generation,higher cost technology may reduce die size for circuitry that scaleswell to be included in the first die 204. Including a second die 206that has a larger footprint than a first die 204, at least in onedimension, may allow for separation of functionality and manufacturingflexibility. In certain examples, a first embedded die 204 may be usedin all manufactured assemblies, but a second die 206 may includedifferent types of functionality or logic, thus allowing for thecreation of different systems.

In certain examples, the first die 204 is an analog die and the seconddie 206 is a digital die. In certain examples, the first die 204 is adigital die and the second die 206 is an analog die. Including an analogdie stacked on a top surface of a digital die may help reduce noise andelectromagnetic interference issues since the analog die may be closerto the external environment and may not be as susceptible to noise orelectromagnetic interference as the digital die.

Device 200 may include at least one first die to substrate connection208 located at an interface between the first die 204 and the packagesubstrate 202. In certain examples, the at least one first die tosubstrate connection 208 may be included in a first level interconnect.In certain examples, the at least one first die to substrate connection208 may be coupled between the first die 204 and the package substratebus 214 a or 214 b.

Device 200 may include at least one second die to substrate connection210 located at an interface between the second die 206 and the packagesubstrate 202. In certain examples, the at least one second die tosubstrate connection 210 may be outside the periphery of the first die204. In certain examples, the at least one second die to substrateconnection 210 may be coupled between the second die 206 and the packagesubstrate bus 214 a or 214 b. In certain examples, the at least onefirst die to substrate connection 208 and second die to substrateconnection 210 may be connections that transfer power or data from thepackage substrate to the first or second die 204 or 206.

Device 200 may include at least one second die to first die connection212 located at an interface between the first and second dice 204 and206. In certain examples, the at least one second die to first dieconnection 212 may be included in a logic to logic interconnect. Incertain examples, the at least one second die to first die connection212 is a data connection that passes data between the first and seconddice 204 and 206.

In certain examples, it may be beneficial to pre-stack first and seconddice 204 and 206 before embedding dice in the package substrate 202. Incertain examples, pre-stacking the dice may be accomplished using a flipchip, wire bonding, or other technique. In certain examples,pre-stacking dice before embedding them in the package substrate may beaccomplished using a thermal compression bonding technique. In certainexamples, pre-stacking first and second dice using thermal compressionbonding may help preserve the dimensions of the dice. In certainexamples, the dice may be pre-stacked and then a bumpless build-up layer(BBUL) package substrate may be built around the pre-stacked dice.

FIG. 3 is an illustration of first and second pre-stacked dice 300. Incertain examples, the first and second dice may be pre-stacked (i.e.stacked before they are embedded in a package substrate) using thermalcompression bonding. In certain examples the first die 204 may includeat least one first die to substrate contact 308 operable to connect thefirst die 204 to a package substrate. In certain examples, the at leastone first die to substrate contact 308 may be included in a first levelinterconnect. In certain examples, the second die 206 includes at leastone second die to substrate contact 310 operable to connect directly toa package substrate. The at least one second die to substrate contact310 may be outside the periphery of the first die 204. In certainexamples, the pre-stacking may create at least one second die to firstdie connection 212 located at an interface between the first and seconddice 204 and 206. In certain examples, the at least one second die tofirst die connection 212 may be included in a logic to logicinterconnect. In certain examples, the second die includes at least onethird die to second die contact 302 operable to connect the second die206 to a third die that may be stacked above a top surface of the seconddie. In certain examples, the at least one third die to second diecontact 302 may be included in a logic to memory interconnect. WhileFIG. 3 shows two dice stacked, it should be appreciated that any numberof dice may be stacked and embedded in accord with the presentdisclosure.

FIG. 4 is an illustration of a device 400 according to an exampleembodiment. Device 400 may include a package substrate with multipleembedded dice 402 and a second package substrate (e.g. third die) 404stacked above a top surface of the substrate with multiple embedded dice402. The package substrate with multiple embedded dice may besubstantially similar to device 200 of FIG. 2. The package substratewith multiple embedded dice 402 may include a second die coupled to atop surface of a first die such as is described with regard to FIG. 2 or3. The package substrate with multiple embedded dice 402 may include atleast one first die to substrate, second die to substrate, and seconddie to first die connection such as is described with regard to FIG. 2.The package substrate with multiple embedded dice 402 may include firstand second busses operable to transmit power or data such as isdescribed with regard to FIG. 2.

Device 400 may include a second package substrate 404 stacked above atop surface of the package substrate with multiple embedded dice 402.The second package substrate 404 may include a third die. In certainexamples, the third die may be a memory. In certain examples, the memorymay be a dual data rate (e.g. DDR2 or DDR3) memory. The stacking of thesecond package substrate 404 above the top surface of the packagesubstrate with multiple embedded dice 402 may create a device 500 with apackage on package architecture. In certain examples, the second packagesubstrate 404 may be connected to the package substrate with multipleembedded dice 402 using a wire bonding, flip chip, or other connectiontechnique.

Device 400 may include at least one second package substrate (e.g. thirddie) to first package substrate connection 408 located at an interfacebetween the second package substrate 404 and the substrate of thepackage substrate with multiple embedded dice 402. The at least onesecond package substrate to first package substrate connection 408 maybe connected between the second package substrate 404 and a bus includedin the package substrate with multiple embedded dice. In certainexamples, the at least one second package substrate to first packagesubstrate connections may be outside the periphery of the second die ofthe package substrate with multiple embedded dice 402. In certainexamples, the at least one second package substrate to first packagesubstrate connection 408 transmits power to the second package substrate404. In certain examples, the at least one second package substrate tofirst package substrate connection 408 transmits data to/from the secondpackage substrate 404.

FIG. 5 is an illustration of a device 500 according to an exampleembodiment. Device 500 may include a package substrate with multipleembedded dice 502 and a second package substrate (e.g. third die) 504stacked above a top surface of the substrate with multiple embedded dice502. The package substrate with multiple embedded dice may besubstantially similar to device 200 of FIG. 2. The package substratewith multiple embedded dice 502 may include a second die coupled to atop surface of a first die such as is described with regard to FIG. 2 or3. The package substrate with multiple embedded dice 502 may include atleast one first die to substrate, second die to substrate, and seconddie to first die connection such as is described with regard to FIG. 2.The package substrate with multiple embedded dice 502 may include firstand second busses operable to transmit power or data such as isdescribed with regard to FIG. 2.

Device 500 may include a second package substrate 504 stacked above atop surface of the package substrate with multiple embedded dice 502.The second package substrate 504 may include a third die. In certainexamples, the third die may be a memory. In certain examples, the memorymay be a dual data rate (e.g. DDR2 or DDR3) memory. The stacking of thesecond package substrate 504 above the top surface of the packagesubstrate with multiple embedded dice 502 may create a device 500 with apackage on package architecture. In certain examples, the second packagesubstrate 504 may be stacked above the package substrate with multipleembedded dice 502 using thermal compression bonding. In certainexamples, the second package substrate 504 may be connected to thepackage substrate with multiple embedded dice 502 using a wire bonding,flip chip, or other connection technique. In certain examples, thesecond package substrate 504 may include a memory device thatcommunicates to the second die using a logic to memory interface such asthe logic to memory interface of FIG. 3. In certain examples the thirddie may communicate to the first die, the second die, or the packagesubstrate, using a ball grid array (BGA) interface. In certain examples,the second package substrate 504 may be coupled to the package substratewith multiple embedded dice 502 at a top surface of the packagesubstrate with multiple embedded dice.

Device 500 may include at least one second package substrate (e.g. thirddie) to second die connection 506 located at an interface between thesecond die of the package substrate with multiple embedded dice 502 andthe second package substrate 504. In certain examples, the device 500may include a logic to memory interface including the at least onesecond package substrate to second die connection 506. The at least onesecond package substrate to second die connection 506 may transmit databetween the second die and the second package substrate 504. In certainexamples, the second package substrate to second die connection 506 maybe configured as a package on package connection.

Device 500 may include at least one second package substrate (e.g. thirddie) to first package substrate connection 508 located at an interfacebetween the second package substrate 504 and the substrate of thepackage substrate with multiple embedded dice 502. The at least onesecond package substrate to first package substrate connection 508 maybe connected between the second package substrate 504 and a bus includedin the package substrate with multiple embedded dice. In certainexamples, the at least one second package substrate to first packagesubstrate connections may be outside the periphery of the second die ofthe package substrate with multiple embedded dice 502. In certainexamples, the at least one second package substrate to first packagesubstrate connection 508 transmits power to the second package substrate504. In certain examples, the at least one second package substrate tofirst package substrate connection 408 transmits data to/from the secondpackage substrate 504.

FIG. 6 illustrates a flow diagram of a method 600 of making a deviceaccording to an example embodiment. Method 600 may include pre-stackingfirst and second dice 602. The first or second die may be primarilyanalog, primarily digital, or a combination thereof. The second die mayinclude a width (e.g. a footprint with a dimension) greater than acorresponding width (e.g. a corresponding dimension of a footprint) ofthe first die. The second die may be stacked above a top surface of thefirst die. The pre-stacking may be accomplished using a flip chipprocess, a wire bonding process, thermal compression bonding process, orother bonding process. At 604 a substrate may be formed around the firstand second dice. The substrate may be a bumpless build-up layersubstrate. At least one second die to substrate connection may be formedat an interface between the second die and the substrate at 606. The atleast one second die to substrate connection may be formed outside theperiphery of the first die. The at least one second die to substrateconnection may be between the second die and a bus included in thesubstrate. The bus may carry power or data signals. At 608 at least onefirst die to substrate connection may be formed at an interface betweenthe first die and the substrate. The at least one first die to substrateconnection may be between the first die and a bus included in thesubstrate.

At 610 a third die (e.g. a second package substrate) may be stackedabove the second die. The third die may be coupled to the second die ata top surface of the second die. The third die may be analog, digital,or a combination thereof. In certain examples, the third die is a memorydie. The third die may include a width greater than the correspondingwidth of the second die. At 612 at least one third die to second dieconnection may be formed at an interface between the third die and thesecond die. The at least one third die to second die connection maytransmit data between the second and third dice. At least one third dieto substrate connection located at an interface between the third dieand the substrate may be formed at 614. The at least one third die tosubstrate connection (e.g. a second substrate package to first substratepackage connection) may be formed outside the periphery of the seconddie. The at least one third die to substrate connection may be betweenthe third die and a bus included in the substrate. At 616 at least onefirst to second die connection may be formed between the first andsecond dice. The at least one second die to first die connection maytransfer data between the first and second dice.

An example of an electronic device using a die as described in thepresent disclosure is included to show an example of a higher leveldevice application for the present disclosure. FIG. 7 is a block diagramof an electronic device 700 incorporating at least one die in accordancewith at least one embodiment of the invention. Electronic device 700 ismerely one example of an electronic system in which embodiments of thepresent invention can be used. Examples of electronic devices 700include, but are not limited to personal computers, tablet computers,mobile telephones, personal data assistants, MP3 or other digital musicplayers, radios, etc. In this example, electronic device 700 comprises adata processing system that includes a system bus 702 to couple thevarious components of the system. System bus 702 provides communicationslinks among the various components of the electronic device 700 and canbe implemented as a single bus, as a combination of busses, or in anyother suitable manner.

An electronic assembly 710 is coupled to system bus 702. The electronicassembly 710 can include any circuit or combination of circuits. In oneembodiment, the electronic assembly 710 includes a processor 712 whichcan be of any type. As used herein, “processor” means any type ofcomputational circuit, such as but not limited to a microprocessor, amicrocontroller, a complex instruction set computing (CISC)microprocessor, a reduced instruction set computing (RISC)microprocessor, a very long instruction word (VLIW) microprocessor, agraphics processor, a digital signal processor (DSP), multiple coreprocessor, or any other type of processor or processing circuit.

Other types of circuits that can be included in electronic assembly 710are a custom circuit, an application-specific integrated circuit (ASIC),or the like, such as, for example, one or more circuits (such as acommunications circuit 714) for use in wireless devices like mobiletelephones, pagers, personal data assistants, portable computers,two-way radios, and similar electronic systems. The IC can perform anyother type of function.

The electronic device 700 can also include an external memory 720, whichin turn can include one or more memory elements suitable to theparticular application such as a main memory 722 in the form of randomaccess memory (RAM), one or more hard drives 724, and/or one or moredrives that handle removable media 726 such as compact disks (CD),digital video disk (DVD), and the like.

The electronic device 700 can also include a display device 716, one ormore speakers 718, and a keyboard and/or controller 730, which caninclude a mouse, trackball, touch screen, voice-recognition device, orany other device that permits a system user to input information intoand receive information from the electronic device 700.

Additional Notes and Examples

In Example 1, a device includes a first die within a package substrate,a second die, having a width greater than the first die, coupled to atop surface of the first die, at least one first die to substrateconnection located at an interface between the first die and the packagesubstrate, and at least one second die to substrate connection locatedat an interface between the second die and the package substrate outsidethe periphery of the first die.

In Example 2, the device of Example 1 includes a second die to first dieconnection located at an interface between the first die and the seconddie.

In Example 3, the second die to first die connection of any one or moreof Examples 1-2 is a data connection.

In Example 4, the first die to substrate and second die to substrateconnection of any one or more of Examples 1-3 are power connections.

In Example 5, the at least one first die to substrate connection of anyone or more of Examples 1-4 include at least one data connection and atleast one power connection.

In Example 6, the first die of any one or more of Examples 1-5 is adigital die.

In Example 7, the second die of any one or more of Examples 1-6 is ananalog die.

In Example 8, the package substrate of any one or more of Examples 1-7is configured as a bumpless build-up layer package substrate.

In Example 9, a device includes a first die embedded within a firstpackage substrate, a second die, having a width greater than the firstdie, coupled to a top surface of the first die, a second die to firstdie connection located at an interface between the first die and thesecond die, a second die to substrate connection located at an interfacebetween the second die and the package substrate outside the peripheryof the first die, a second package substrate, having a width greaterthan the second die, coupled to a top surface of the second die, and asecond package substrate to first package substrate connection locatedat an interface between the second package substrate and the firstpackage substrate outside the periphery of the second die.

In Example 10, the device of any one or more of Examples 1-9 includes asecond package substrate to second die connection located at aninterface between the second die and the second package substrate.

In Example 11, the second package substrate of any one or more ofExamples 1-10 is a memory die.

In Example 12, the second package substrate to second die connection ofany one or more of Examples 1-11 is a dual data rate connection.

In Examples 13, the second die to first die connection of any or more ofExamples 1-12 is a data connection.

In Example 14, the first and second dice of any one or more of Examples1-13 are digital and analog, respectively.

In Example 15, the first package substrate of any one or more ofExamples 1-14 is configured as a bumpless build-up layer substrate.

In Example 16, the second die of any or more of Examples 1-15 isembedded in the first package substrate.

In Example 17, a device includes a first die embedded within a firstpackage substrate, a second die embedded within the first packagesubstrate, wherein the second die includes a width greater than thefirst die and is coupled to a top surface of the first die, a first dieto second die connection located at an interface between the first dieand the second die, a second die to substrate connection located at aninterface between the second die and the first package substrate outsidethe periphery of the first die, a second package substrate having awidth greater than the second die coupled to a top surface of the seconddie, and a second package substrate to first package substrateconnection located at an interface between the first package substrateand the second package substrate outside the periphery of the seconddie.

In Example 18, the first package substrate of any one or more ofExamples 1-17 is configured as a bumpless build-up layer substrate.

In Example 19, the second package substrate of any one or more ofExamples 1-18 is configured as a bumpless build-up layer substrate.

In Example 20, the device of any one or more of Examples 1-19 includes asecond package substrate to second die connection located at aninterface between the second die and the second package substrate.

In Example 21, the second package substrate to second die connection ofany one or more of Examples 1-20 is configured as a package on packageconnection.

In Example 22, the first die, the second die, and the second packagesubstrate of any one or more of Examples 1-21 is a digital die, ananalog die, and a memory package, respectively.

In Example 23, a method includes pre-stacking first and second dice,wherein the second die includes a width greater than the first die, andwherein the second die is stacked above the first die, forming a firstpackage substrate around the first and second dice, and forming a seconddie to substrate connection located at an interface between the seconddie and the first package substrate outside the periphery of the firstdie.

In Example 24, forming the first package substrate of any one or more ofExamples 1-23 includes forming a bumpless build-up layer substrate.

In Example 25, pre-stacking of first and second dice of any one ofExamples 1-24 includes thermal compression bonding.

In Example 26, the method of any one or more of Examples 1-25 includesforming a first die to substrate connection located at an interfacebetween the first die and the first package substrate.

In Example 27, the method of any one or more of Examples 1-26 includesstacking a second package substrate on the second die, wherein thesecond package substrate includes a width greater than the second die,forming a second package substrate to second die connection located atan interface between the second die and the second package substrate,and forming a second package substrate to first package substrateconnection located at an interface between the first package substrateand the second package substrate outside the periphery of the seconddie.

The above detailed description includes references to the accompanyingdrawings, which form a part of the detailed description. The drawingsshow, by way of illustration, specific embodiments in which theinvention can be practiced. These embodiments are also referred toherein as “examples.” Such examples can include elements in addition tothose shown or described. However, the present inventors alsocontemplate examples in which only those elements shown or described areprovided. Moreover, the present inventors also contemplate examplesusing any combination or permutation of those elements shown ordescribed (or one or more aspects thereof), either with respect to aparticular example (or one or more aspects thereof), or with respect toother examples (or one or more aspects thereof) shown or describedherein.

In this document, the terms “a” or “an” are used, as is common in patentdocuments, to include one or more than one, independent of any otherinstances or usages of “at least one” or “one or more.” In thisdocument, the term “or” is used to refer to a nonexclusive or, such that“A or B” includes “A but not B,” “B but not A,” and “A and B,” unlessotherwise indicated. In this document, the terms “including” and “inwhich” are used as the plain-English equivalents of the respective terms“comprising” and “wherein.” Also, in the following claims, the terms“including” and “comprising” are open-ended, that is, a system, device,article, composition, formulation, or process that includes elements inaddition to those listed after such a term in a claim are still deemedto fall within the scope of that claim. Moreover, in the followingclaims, the terms “first,” “second,” and “third,” etc. are used merelyas labels, and are not intended to impose numerical requirements ontheir objects.

The above description is intended to be illustrative, and notrestrictive. For example, the above-described examples (or one or moreaspects thereof) may be used in combination with each other. Otherembodiments can be used such as by one of ordinary skill in the art uponreviewing the above description. The Abstract is provided to comply with37 C.F.R. §1.72(b), to allow the reader to quickly ascertain the natureof the technical disclosure. It is submitted with the understanding thatit will not be used to interpret or limit the scope or meaning of theclaims. Also, in the above Detailed Description, various features may begrouped together to streamline the disclosure. This should not beinterpreted as intending that an unclaimed disclosed feature isessential to any claim. Rather, inventive subject matter may lie in lessthan all features of a particular disclosed embodiment. Thus, thefollowing claims are hereby incorporated into the Detailed Description,with each claim standing on its own as a separate embodiment, and it iscontemplated that such embodiments can be combined with each other invarious combinations or permutations. The scope of the invention shouldbe determined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

What is claimed is:
 1. A device, comprising: a first die within apackage substrate; a second die within the package substrate, the seconddie having a width greater than the first die, and the second diecoupled to a top surface of the first die; at least one first die tosubstrate connection located at an interface between the first die andthe package substrate and entirely within the periphery of the firstdie, wherein the first die to substrate connection includes anelectrical coupling between the first die and a power bus; and a seconddie to substrate connection located at an interface between the seconddie and the package substrate outside the periphery of the first die andentirely within the periphery of the second die, wherein the second dieto substrate connection electrically couples the second die to the powerbus using a single via.
 2. The device of claim 1, wherein the devicecomprises a first die to second die connection located at an interfacebetween the first die and the second die and entirely within theperiphery of the first die, wherein the first die to second dieconnection is an electrical connection.
 3. The device of claim 2,wherein the first die to second die connection is a data connection. 4.The device of claim 1, wherein the at least one first die to substrateconnection includes at least one data connection.
 5. The device of claim1, wherein the first die is digital.
 6. The device of claim 1, whereinthe second die is analog.
 7. The device of claim 1, wherein the packagesubstrate is configured as a bumpless build-up layer package substrate.8. A device, comprising: a first die embedded within a first packagesubstrate; a second die, having a width greater than the first die,coupled to a top surface of the first die; a second die to first dieelectrical connection located at an interface between the first die andthe second die and entirely within the periphery of the first die; asecond die to first package substrate connection located between thesecond die and the first package substrate outside the periphery of thefirst die and entirely within the periphery of the second die, whereinthe second die to substrate connection electrically couples the seconddie to a power bus using a single via; a second package substrate,having a width greater than the second die, coupled to a top surface ofthe second die; and a second package substrate to first substratepackage connection located at an interface between the second packagesubstrate and the first package substrate outside the periphery of thesecond die, wherein the second substrate to first substrate packageconnection electrically couples the second substrate to the power bus.9. The device of claim 8, comprising a second package substrate tosecond die connection located at an interface between the second die andthe second package substrate and entirely within the periphery of thesecond die.
 10. The device of claim 8, wherein the second packagesubstrate includes a memory die.
 11. The device of claim 10, wherein thesecond package substrate to second die connection is a dual data ratedata connection.
 12. The device of claim 8, wherein the first die tosecond die connection is a data connection.
 13. The device of claim 8,wherein the first die is digital and the second die is analog.
 14. Thedevice of claim 8, wherein the first package substrate is configured asa bumpless build-up layer package substrate.
 15. The device of claim 8,wherein the second die is embedded in the first package substrate.
 16. Adevice, comprising: a first die embedded within a first packagesubstrate; a second die embedded within the first package substrate,wherein the second die includes a width greater than the first die andis coupled to a top surface of the first die; a second die to firstpackage substrate connection located at an interface between the seconddie and the first package substrate outside the periphery of the firstdie and entirely within the periphery of the second die, wherein thesecond die to first package substrate connection electrically couplesthe second die to a power bus using a single via; a first die to seconddie connection located at an interface between the first die and thesecond die, wherein the first die to second die connection is anelectrical connection; a second package substrate, having a widthgreater than the second die coupled to a top surface of the second die;and a second package substrate to first package substrate connectionlocated at an interface between the first package substrate and thesecond package substrate outside the periphery of the second die,wherein the second package substrate to first package substrateconnection electrically couples the second package substrate to thepower bus.
 17. The device of claim 16, wherein the first packagesubstrate is a bumpless build-up layer substrate.
 18. The device ofclaim 17, wherein the second package substrate is a bumpless build-uplayer substrate.
 19. The device of claim 17, wherein the second packagesubstrate to second die connection is configured as a package on packageconnection.
 20. The device of claim 16, comprising a second packagesubstrate to second die connection located at an interface between thesecond die and the second package substrate and entirely within theperiphery of the second die.
 21. The device of claim 16, wherein thefirst die is digital, the second die is analog, and the second packageis a memory package.
 22. A method comprising: pre-stacking first andsecond dice, wherein the second die includes a width greater than thefirst die, and wherein the second die is stacked above the first die;forming a first die to second die connection located at an interfacebetween the first die and the second die, wherein the first die tosecond die connection is an electrical connection; forming a firstpackage substrate around the first and second dice; and forming a seconddie to substrate connection located at an interface between the seconddie and the first package substrate outside the periphery of the firstdie and entirely within the periphery of the second die, wherein thesecond die to substrate connection electrically couples the second dieto a power bus using a single via.
 23. The method of claim 22, whereinforming the first package substrate includes forming a bumpless build-uplayer substrate.
 24. The method of claim 22, wherein pre-stacking firstand second dice includes thermal compression bonding.
 25. The method ofclaim 22, comprising forming a first die to substrate connection locatedat an interface between the first die and the first package substrate,wherein the first die to substrate connection electrically couples thefirst die to the power bus using single via.
 26. The method of claim 22,comprising: stacking a second package substrate above a top surface ofthe second die, wherein the second package substrate includes a widthgreater than the second die; forming a second package substrate tosecond die connection located at an interface between the second packagesubstrate and the second die; and forming a second package substrate tofirst package substrate connection located at an interface between thesecond package substrate and the first package substrate outside theperiphery of the second die, wherein the second package substrate tofirst package substrate connection electrically couples the secondpackage substrate to the power bus.